1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com hv632 features hvcmos ? technology 5.0v cmos inputs output voltage up to +80v pwm gray shade conversion capable of 256 levels of gray shading 10mhz shift and count clock frequency 20mhz data throughput rate 8 bit data bus 32 outputs per device blank function output polarity control applications field emission displays (fed) polymer liquid crystal displays (plcd) vacuum fluorescent displays (vfd) ? ? ? ? ? ? ? ? ? ? ? ? ? ? typical application circuit 32-channel, 256 gray-shade high voltage driver general description the hv632 is a 32-channel gray-shade column driver ic designed for driving electro?uorescent displays. using supertexs unique hvcmos ? technology, it is capable of 256 levels of gray shading by pwm conversion. input data, in groups of eight, is latched into a set of data latches on both edges of the shift clock. the data shifted in the ?rst data latch corresponds to hv out 1, the second data latch corresponds to hv out 2, and so on. these data are compared to the contents of the master binary counter which counts on both edges of the count clock. each time the master counter begins to decrement from 1111 1111, the data in the data latches are compared with the contents of the counter; if they match, the corresponding outputs will go high. the master counter counts down to 00000001 and then starts to count up again. the outputs that are at high will stay at high until the contents of the counter match the data in the data latches again. therefore, the higher the binary data in the data latches, the longer the outputs will stay at high. thus, different high voltage pulse widths are produced. when the counter reaches its 1111 1111 count while counting up, the device is ready for the next operation cycle. a data value of 0000 0000 produces no pulse; the output stays low. the blank input signal will reset the master counter to all ones (1111 1111) and set all high voltage outputs to low, or will set all high voltage outputs to high state, when the pol is low. the pol input signal, forced low, will invert the polarity of the output pulse. if left unconnected, pol input will be pulled high to v dd by an on-chip resistor. d in (1-8) sc cso csi lc bl cc shift register hv out 32 co lu nm s (c at ho des ) hv632 csi for cascading the next hv632 pol 32 micro processor low vo ltag e latches counter comparators level t ranslators & push-pull output buf fers high v oltage hv out 1 scan driver hv5790 8 displa y pane l (fed ) low v oltag e power supply high v oltag e power supply
2 hv632 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com ordering information device 64-lead pqfp 20.00x14.00mm body 3.40mm height (max) 0.80mm pitch 3.90mm footprint hv632 HV632PG-G -g indicates package is rohs compliant (green) absolute maximum ratings parameter value supply voltage, v dd -0.5v to +7.5v supply voltage, v pp -0.5v to +90v logic input levels -0.5v to v dd +0.5v continuous total power dissipation 1 1200mw operating temperature range -40c to +85c storage temperature range -65c to +150c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. note: for operation above 25c ambiant derate linearly to 85c at 20mw/c 1. recommended operating conditions sym parameter min max units v dd logic supply voltage 4.5 5.5 v v pp positive high voltage supply 12 80 v v il low-level input voltage 0 1.0 v v ih high-level input voltage v dd -1 v dd v t a operating temperature -40 +85 c pin con?guration 1 64 product marking l = lot number yy = year sealed ww = week sealed c = country of origin a = assembler id = green packagin g top marking h v 6 3 2 p g l l l l l l l l l l y y w w c c c c c c c c a a a 64-lead pqfp (pg) 64-lead pqfp (pg) (top view) electrical characteristics (over recommended operating conditions of v dd = 5.0v, v pp = 80v, and t a = 25c unless noted) low voltage dc characteristics (digital) sym parameter min max units conditions v dd low voltage digital supply voltage 4.5 5.5 v --- i dd v dd supply current - 25 ma f sc = 10mhz, f cc = 10mhz i ddq quiescent v dd supply current - 150 a all v in = gnd, count clock = v dd i ih high-level input current - 10 a v in = v dd i il low-level input current - -10 a v il = gnd package may or may not include the following marks: si or
3 hv632 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com sym parameter min max units conditions i oh high level output current -1.0 - ma v out = 0.9v dd i ol low level output current 1.0 - ma v out = 0.1v dd high voltage dc characteristics i ppq quiescent v pp supply current - 100 a all hv out low or high i out(p) p-channel output current -4.0 - ma hv out = 75v i out(n) n-channel output current 4.0 - ma hv out = 5.0v i pp v pp supply current - 1.1 ma c l = 0pf, f cc =10mhz ac characteristics f sc shift clock frequency - 10 mhz --- f cc count clock frequency - 10 mhz --- f din data in frequency - 20 mhz --- t cw chip select pulse width 80 - ns --- t css chip select to shift clock set-up time 5.0 - ns --- t csh chip select to shift clock hold time 15 - ns --- t scc shift clock cycle time 100 - ns --- t dss data to shift clock set-up time 10 - ns --- t dsh data to shift clock hold time 40 - ns --- t dw data in pulse width 50 - ns --- t lcw load count pulse width 75 - ns --- t ccw count clock pulse width 50 - ns --- t ccc count clock cycle time 100 - ns --- t lcd load count to count clock delay 100 - ns --- t ccd count clock to hv out turn-on/turn-off - 300 ns c l = 15pf t blw blank pulse width 700 - ns --- t bld blank to hv out delay - 500 ns c l = 15pf t cdd count clock delay between count down and count up cycles 150 - ns --- t csoh cso delay output for high - 40 ns c l = 15pf t csol cso delay output for low - 40 ns c l = 15pf electrical characteristics (over recommended operating conditions of v dd = 5.0v, v pp = 80v, and t a = 25c unless noted) low voltage dc characteristics (digital) (cont.)
4 hv632 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com functional block diagram > 8 8 > 8 8 > 8 8 > 8 > 8 hv out 1 hv out 2 hv out 3 hv out 32 ? ? ? vpp vpp 8 bit data in 8 > > > > > count clock blank l/t = level t ranslator c so cs i hv gnd > hv gnd > load c ount s hift c lock p o l* * internal pull-up resistor d ata latch 1 c omparato r & latch 1 l/t d ata latch 2 c omparato r & latch 2 l/t d ata latch 3 c omparato r & latch 3 l/t d ata latch 32 c omparato r & latch 32 l/t logi c 8 bit c ounter logic logic logic logic input and output equivalent circuits vdd input gnd vpp hvgnd hv out logic inputs gnd data out logic data output high v oltage output vdd
5 hv632 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com timing diagrams t cw t css dat a set 1 t dss t dsh t dw loading last devic e next loading cycl e csi shif t clock load count count clock count clock hv out t sc c sc 1 50 % t csh 50 % 50% sc2 s c16 s c1 sc n dat a set 2 dat a set 3 data set 31 data set 32 data set 1 t lcw t cc w t cc c t lcd v ih v il v ih v il v ih v il v ih v il v ih v il 50% 50% 90% 10% 10% 50 % 50% 50% 50 % t ccd data set 2 data set 2n -1 blan k t bl w t cd d v ih v il 50% 50 % 255 254 3 3 2 2 1 1 90% hv out t bld v pp hv gn d v il 50% 50% v ih data 1C 8 v pp hv gn d data set 2n 50% 90 % t cc d t csoh t csol cso v ih v il hv out shift clock 1 2 3 4 16 va lid d ata 1 2 3 4 16 csi cso lc count clock 1 1 25 2 253 25 4 255 255 254 253 252 1 1 25 2 253 25 4 255 255 254 253 252 va lid d ata
6 hv632 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com gray shade decoding scheme shade number d8 d7 d6 d5 d4 d3 d2 d1 256 1 1 1 1 1 1 1 1 255 1 1 1 1 1 1 1 0 254 1 1 1 1 1 1 0 1 253 1 1 1 1 1 1 0 0 252 1 1 1 1 1 0 1 1 251 1 1 1 1 1 0 1 0 250 1 1 1 1 1 0 0 1 249 1 1 1 1 1 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 7 0 0 0 0 0 1 1 0 6 0 0 0 0 0 1 0 1 5 0 0 0 0 0 1 0 0 4 0 0 0 0 0 0 1 1 3 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 sequence function data in (d1 - d8) csi cso shift clock load count count clock hv out 1 shift data from hv out 1 to hv out 32 h - output - l l l l h 2 load shift register x pre-de?ne by 1 or 2 - l l - 3 load counter x l - l - 4 counting/voltage conversion x l l - - function table blank polarity table blank polarity hv out 0 0 current output state. 0 1 inverts current output state. 1 0 sets all outputs high. 1 1 sets all outputs low. gray scale voltage 0 hv out hv out hv out hv out hv out 1 2 256 gray scale v oltage clock cycle (0000 0000) ( 1111 1111 )
7 hv632 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com pin descriptions pin # function description 1 nc no connect 2 nc 3 nc 4 hv out 17 high-voltage outputs 5 hv out 18 6 hv out 19 7 hv out 20 8 hv out 21 9 hv out 22 10 hv out 23 11 hv out 24 12 hv out 25 13 hv out 26 14 hv out 27 15 hv out 28 16 hv out 29 17 hv out 30 18 hv out 31 19 hv out 32 20 gnd digital ground 21 gnd 22 hvgnd high voltage ground 23 vpp positive high-voltage supply 24 csi chip select input to enable the device to accept data 25 cso chip select output to enable the next device 26 blank input to reset the counter and hvout 27 d1 inputs for binary-format parallel data (d8 is the most signi?cant bit) 28 d2 29 d3 30 d4 31 count clock input to the counter 32 pol output polarity control 33 load count input to initiate the counting
8 hv632 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com pin # function description 34 shift clock triggers data on both edges 35 nc no connect 36 d5 inputs for binary-format parallel data (d8 is the most signi?cant bit) 37 d6 38 d7 39 d8 40 vdd low-voltage digital supply voltage 41 nc no connect 42 nc 43 vpp positive high-voltage supply 44 hvgnd high voltage ground 45 nc no connect 46 hv out 1 high-voltage outputs 47 hv out 2 48 hv out 3 49 hv out 4 50 hv out 5 51 hv out 6 52 hv out 7 53 hv out 8 54 hv out 9 55 hv out 10 56 hv out 11 57 hv out 12 58 hv out 13 59 hv out 14 60 hv out 15 61 hv out 16 62 nc no connect 63 nc 64 nc pin descriptions
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate product liability indemnification insurance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. website: http//www .supertex.com . ?2009 all rights reserved. unauthorized use or reproduction is prohibited . 1235 bordeaux drive, sunnyvale, ca 94089 te l: 408-222-8888 www .supertex.com 9 hv632 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www.supertex.com/packaging.htm l .) doc.# dsfp-hv632 a042709 64-lead pqfp (3-sided) package outline (pg) 20.00x14.00mm body, 3.40mm height (max), 0.80mm pitch, 3.90mm footprint symbol a a1 a2 b d d1 e e1 e l l1 l2 l3 1 dimen - sion (mm) min 2.80 0.25 2.55 0.30 22.25 19.80 17.65 13.80 0.80 bsc 0.73 1.95 ref 0.25 bsc 0.55 ref 0 o 5 o nom - - 2.80 - 22.50 20.00 17.90 14.00 0.88 3.5 o - max 3.40 0.50 3.05 0.45 22.75 20.20 18.15 14.20 1.03 7 o 16 o drawings not to scale. supertex doc. #: dspd-64pqfppg, version nr090608. note: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. the leads on this side are trimmed. 1. 2. 1 64 seating plane gauge plane l l1 l2 vi ew b vi ew b 1 b e side v iew a2 a a1 e e1 d d1 seating plane to p v iew note 1 (index area d1/4 x e1/4) l3 note 2
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